As the integration density of integrated circuits continues to increase, the size of Field Effect Transistors (FET), such Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), implemented in such integrated circuits may also decrease. However, a decrease in the size of a MOSFET may reduce the MOSFET's channel length. As appreciated by those skilled in the art, a reduction in the MOSFET's channel length may cause a “short channel effect” (SCE) which may increase the likelihood of a phenomenon known as “punch through” between a source and a drain of the MOSFET.
Short channel effects may arise when the depletion region widths of the source and drain junctions become comparable to the channel length. As a result, the potential distribution in the channel may become two-dimensional which can result in large values of sub-threshold current, a decrease in threshold voltage, and/or non-saturation of drain current due to punch through. Punch through may occur when the sum of the source and drain depletion widths exceed the channel length, thereby causing the channel to be punched through (i.e., the depletion region punches through the neutral n-region) when voltage is applied. Thus, since “short channel effects” may complicate device operation and may degrade device performance, it may be desirable to reduce these effects.
In order to reduce the SCE and “punch through”, semiconductor devices have been produced using a technique conventionally known as Selective Epitaxial Growth (SEG). SEG may be used to form an epitaxial layer having an elevated source/drain structure. However, using SEG may result in the formation of a “facet” at the edge of the epitaxial layer. During subsequent ion implantation and thermal treatment, that are used when forming source/drain impurity regions, these facets may cause the electrical characteristics of the resultant semiconductor devices to deteriorate. Problems with the conventional SEG techniques will now be further discussed with reference to FIG. 1.
FIG. 1 shows a cross-sectional view of an FET having an elevated source/drain structure fabricated using conventional SEG techniques. A gate pattern including a gate oxide film 55, a gate electrode 57 and gate spacers 61 are formed on an integrated circuit substrate such as a silicon semiconductor substrate 51 in which an isolation film 53 has been formed by trench isolation. An epitaxial layer 59 is then formed by an SEG process on both sides of the gate pattern and on areas of the semiconductor substrate 51. When ion implantation is performed using the gate pattern as an ion implantation mask, and thermal treatment is performed to activate implanted impurities, an impurity profile 63 is formed in the source/drain region. One problem with this conventional process for fabricating an FET is the formation of a facet A at the edge of the epitaxial layer 59. Such a facet A may undesirably result the formation of a non-uniform impurity region B in the impurity profile 63 at the source/drain region. As shown in FIG. 1, this non-uniform impurity region B has a locally-deep junction which can increase the likelihood of “short channel effects” in the FET which can in turn cause “punch through”. As discussed above, these problems may ultimately degrade the electrical characteristics of the semiconductor device.
One method for fabricating an FET was disclosed in U.S. Pat. No. 4,998,150 to Rodder et al., entitled “RAISED SOURCE/DRAIN TRANSISTOR.” According to this method, a raised source/drain transistor is provided having thick sidewall spacing insulators adjacent the transistor gate. A first sidewall spacer is disposed adjacent thin sidewall spacing insulator and raised source/drain region. A second sidewall spacer is formed at the interface between field insulating region and raised source/drain region. Unfortunately, the area occupied by the source/drain region may be reduced by the area occupied by the additional sidewall spacer which may, in turn, influence the impurity profile that is formed in the source/drain region. Moreover, this method may be complicated since an additional process step for forming the additional sidewall spacer may need to be performed.